The present invention relates generally to a nonvolatile memory device and a method for controlling the same, and more specifically, to a technology for controlling an incremental step pulse program (ISPP) operation in a flash memory device.
Semiconductor memory devices are memory devices configured to store data and read the stored data when necessary. Generally, semiconductor memory devices may include volatile memory devices and nonvolatile memory devices.
Volatile memory devices lose stored data in the absence of supplied power. In such volatile memory devices, data reading and writing speeds are fast, but the stored data is erased when the device is not powered.
Nonvolatile memory devices maintain stored data even when not powered. Thus, the nonvolatile memory devices are used to preserve data regardless of power supply.
Examples of nonvolatile memory devices may include a mask read-only memory (MROM) device, a programmable read-only memory (PROM) device, an erasable and programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, and a flash memory device.
In MROM, PROM and EPROM devices, an erase operation and a writing operation are not flexible, and it is difficult for general users to change memorized contents. On the other hand, the erase and writing operations can be electrically performed in an EEPROM device. Thus, the EEPROM device has been applied to system programming which requires continuous renewal or has been widely used as a subsidiary memory device.
Since flash memory devices have a higher degree of integration than a conventional EEPROM device, they are particularly advantageous in the application to subsidiary memory devices of high capacity. Of these flash memory devices, a NAND-type flash memory device has a very high degree of integration.
In the flash memory device, data writing and erase operations are electrically performed. A memory cell array of the flash memory device includes a plurality of blocks, each block includes a plurality of pages, and each page includes a plurality of memory cells. The block is a minimum unit to erase data stored in the memory cell array.
In a program or erase operation, the flash memory device employs a tunneling effect, to allow carriers to pass through a high energy barrier, and a hot carrier effect, to allow hot carriers having a high moving energy to pass through an insulating material.
Such a program or erase operation is a factor that limits the amount of data to be recorded in flash memory cells and causes mis-operation of flash memory cells in a data writing operation.
Also, defects may be generated in the flash memory cells by a plurality of restraints in a manufacturing process of a flash memory device that requires a high degree of integration.
In a NAND-type flash memory device, when data is written in a memory cell, a previously stored marginal value level of the memory cell may be changed by a mis-operation or a write effect of adjacent cells. If the previously stored marginal value level is changed, the accuracy of data may be degraded.
Moreover, a program progress speed in a block may vary for each page even in one chip when a program operation is performed. In another chip, such program progress speed may vary depending on a manufacturing process and characteristics of the device.